SREE VIDYANIKETHAN ENGINEERING COLLEGE Sree Sainath Nagar, Tirupati- 517 102 YEAR 2007 – 2008 TIME – TABLE II B.Tech. I Semester Electronics & Communication Engineering Section ‘A'
Room No. 331 w.e.f: 11-08-2007
Day \ Hour
10:30AM – 11:20AM
11:20AM – 12:10PM
12:10PM – 01:00PM
L U N C H
B R E A K
02:15PM – 03:05PM
03:05PM – 03:55PM
03:55PM – 04:45PM
1
2
3
4
5
6
Mon
ECA
SS
PTSP (TUT)
PDC/EC Lab
Tue
PTSP
PDC
M-III
ES
SS (TUT)
Wed
ES (TUT)
Thu
PDC (TUT)
Fri
ECA (TUT)
Sat
M-III (TUT)
Signals & Systems
Mr. M. Naseer Ahammad
Pulse & Digital Circuits
Ms. R.V. Kanaka Durga
Probability Theory & Stochastic Process
Ms. D. Leela Rani
Electronic Circuit Analysis
Mr. M. Sivasubramanyam
Mathematics – III
Dr. A. V. M. Prasad
Environmental Studies
Mr. M. Ramachandraiah
ECA Lab
Electronic Circuit Lab
Mr. M. Sivasubramanyam/ Ms. K. Neelima
PDC Lab
Pulse & Digital Circuits Lab
Ms. R.V. Kanaka Durga/ Ms. B. Prathima
TUT – Tutorial Class.
Head, Dept. of ECE DEAN (Academic)
SREE VIDYANIKETHAN ENGINEERING COLLEGE Sree Sainath Nagar, Tirupati- 517 102 YEAR 2007 – 2008 TIME – TABLE II B.Tech. I Semester Electronics & Communication Engineering Section ‘B'
Room No. 332 w.e.f: 11-08-2007
Dr. T. Venkateswarlu
Ms. G. Komala Yadav
Mr.P. V. Satyanarayana
Ms. M. V. K. Sreedevi
Mr. M.Sivasubramanyam/ Ms. K. Neelima